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TABLE OF CONTENTS

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XC5200 Family Compared to XC4000 Family . . . . . . . . . . . . . . . . . . . . . . . . .

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VersaBlock Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Routing Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XC5200
Logic Cell Array Family

Preliminary (v1.0)

Product Description

Table 1.

Initial XC5200 Field-Programmable Gate Array Family Members

Device

XC5202

XC5204

XC5206

XC5210

XC5215

Typical Gate Range

2,200 -
2,700

3,900 -
4,800

6,000 -
7,500

10,000 -
12,000

14,000 -
18,000

VersaBlock Array

8 x 8

10 x 12

14 x 14

18 x 18

22 x 22

Number of CLBs

120

196

324

484

Number of Flip-Flops

256

480

784

1,296

1,936

Number of I/Os

124

148

196

244

TBUFs per Horizontal Longline

· Fully supported by XACT

Development System

-- Includes complete support for XACT-PerformanceTM,

X-BLOXTM, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XCheckerTM

-- Wide selection of PC and workstation platforms
-- Interfaces to more than 100 third-party CAE tools

Description

The XC5200 Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200 architecture for TLM
technology and 0.6-

m CMOS SRAM process, dramatic

advances have been made in silicon efficiency. These
advances position the XC5200 family as a cost-effective,
high-volume alternative to gate arrays.

Building on experiences gained with three previous
successful SRAM FPGA families, the XC5200 family
brings a robust feature set to high-density programmable
logic design. The VersaBlock logic module, the VersaRing
I/O interface, and a rich hierarchy of interconnect
resources combine to enhance design flexibility and
reduce time-to-market.

Complete support for the XC5200 family is delivered
through the familiar XACT software environment. The
XC5200 family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and
synthesis. Designers utilizing logic synthesis can use their
existing Synopsys, Viewlogic, Mentor, and Exemplar tools
to design with the XC5200 devices.

Features

· High-density family of Field-Programmable Gate Arrays

(FPGAs)

· Design- and process-optimized for low cost

-- 0.6-

m three-layer metal (TLM) process

· System performance up to 50 MHz

· SRAM-based, in-system reprogrammable architecture

· Flexible architecture with abundant routing resources

-- VersaBlockTM logic module
-- VersaRingTM I/O interface
-- Dedicated cell-feedthrough path
-- Hierarchical interconnect structure
-- Extensive registers/latches
-- Dedicated carry logic for arithmetic functions
-- Cascade chain for wide input functions
-- Dedicated IEEE 1149.1 boundary-scan logic
-- Internal 3-state bussing capability
-- Four global low-skew clock or signal distribution nets
-- Globally selectable CMOS or TTL input thresholds
-- Output slew-rate control
-- 8-mA sink current per output

· Configured by loading binary file

-- Unlimited reprogrammability
-- Six programming modes, including high-speed

ExpressTM mode

· 100% factory tested

· 100% footprint compatibility for common packages

XC5200 Logic Cell Array Family

Preliminary (v1.0)

XC5200 Family Compared to XC4000 Family

For those readers already familiar with the XC4000 family
of Xilinx Field-Programmable Gate Arrays, here is a
concise description of the similarities and differences
between the XC4000 and XC5200 families.

Superficially, the XC5200 family is quite similar to the
XC4000 family. Both use CMOS SRAM technology. Both
use 4-input lookup tables with unshared inputs. Both have
a dedicated fast carry track, and dedicated boundary-scan
logic in the input/output blocks (IOBs).

XC5200 and XC4000 devices are footprint and pin-out
compatible; their pin names and pin locations are
identical. XC5200 devices offer the same configuration
options as XC4000 devices, and they can be intermixed
with XC4000 devices in a configuration daisy chain.

There are also, however, significant differences between
the two families:

· XC5200 lookup tables cannot be used as RAM.

· The XC5200 family offers dedicated carry logic, but

differs from the XC4000 family in that the sum is
generated in an additional function generator in the
adjacent column. An XC5200 device thus uses twice as
many function generators for adders, subtracters,
accumulators, and some counters. Note, however, that
a loadable up/down counter requires the same number
of function generators in both families.

· XC5200 devices have no dedicated wide edge

decoders. The XC5200 carry logic, unlike the XC4000
architecture, can be used to cascade function
generators to implement wide AND and OR functions,
for example.

· The XC5200 family contains a flexible coupling of logic

and local routing resources called the VersaBlock. The
XC5200 VersaBlock element includes the Configurable
Logic Block (CLB), a Local Interconnect Matrix (LIM),
and direct connects to neighboring VersaBlocks.

· XC5200 CLBs are roughly equivalent to two XC4000

CLBs. Each XC5200 CLB contains four 4-input function
generators and four registers, which are configured as
four independent Logic CellsTM (LCs). The output from
each function generator can be brought out as a CLB
output and/or drive the D input of a flip-flop. Pairs of
logic cells can be combined to form a 5-input function
generator.

· There are four direct feedthrough paths per CLB, one

per LC. These paths can provide extra data input lines
or serve as local routes without consuming any logic
resources.

· The XC5200 family has a global reset, whereas the

XC4000 family has both a global set and a global reset.

· Unlike the XC4000 family, each register can be

configured as either an edge-triggered D flip-flop or a
transparent, level-sensitive latch.

· There are no dedicated IOB flip-flops, but there are fast

direct connects to adjacent CLBs.

Table 2.

Four Generations of Xilinx Field-Programmable Gate Array Families

Parameter

XC5200

XC4000

XC3000A/XC3100A

XC2000

Function generators per CLB

Logic inputs per CLB

Logic outputs per CLB

Low-skew global buffers

User RAM

yes

Dedicated decoders

yes

Cascade chain

yes

Fast carry logic

yes

Internal 3-state drivers

yes

IEEE boundary scan

yes

Output slew-rate control

yes

Power-down option

yes

Crystal oscillator circuit

yes

· The TLM process allows significant improvements in the

routing structure. Each XC5200 VersaBlock element
has complete intra-CLB routing, the LIM, and offers four
direct routing connections to each of the four
neighboring CLBs (North, South, East, and West). Any
function generator or flip-flop thus has unrestricted
connectivity to 19 other function generators or flip-
flops: three in its own CLB, and 16 in the adjacent
CLBs. These direct connects do not compete with the
general routing resources (see Table 3).

· Each XC5200 3-state buffer (TBUF) can drive up to two

horizontal Longlines; each XC4000 TBUF accesses
only one horizontal Longline.

· There is a special racetrack, the VersaRing, between

the outer edge of the core CLB array and the ring of
IOBs, providing significant help in overcoming the
problems caused by early locking of I/O pins.

· There are no internal pull-ups for XC5200 Longlines.

Figure 1.

XC5200 Architectural Overview

Table 3.

Routing Resource Comparison

Resource

XC5200

XC4000

Single-length Lines

Double-length Lines

Longlines

Direct Connects

VersaRing

yes

X4955

GRM

Input/Output Blocks (IOBs)

Versa-

Block

GRM

Versa-

Block

VersaRing

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

GRM

Versa-

Block

VersaRing

Architectural Overview

Figure 1 presents a simplified, conceptual overview of the
XC5200 architecture. Similar to conventional FPGAs, the
XC5200 family consists of programmable IOBs,
programmable logic blocks, and programmable
interconnect. Unlike other FPGAs, however, the logic and
local routing resources of the XC5200 family are
combined in flexible VersaBlocks. General-purpose
routing connects to the VersaBlock through the General
Routing Matrix (GRM).

VersaBlock: Abundant Local Routing Plus Versatile
Logic

The basic logic element in each VersaBlock structure is
the Logic Cell, shown in Figure 2. Each LC contains a 4-
input function generator (F), a storage device (FD), and
control logic. There are five independent inputs and three
outputs to each LC. The independence of the inputs and
outputs allows the software to maximize the resource
utilization within each LC. Each Logic Cell also contains a
direct feedthrough path that does not sacrifice the use of
either the function generator or the register; this feature is
a first for FPGAs. The storage device is configurable as
either a D flip-flop or a latch. The control logic consists of
carry logic for fast implementation of arithmetic functions,
which can also be configured as a cascade chain allowing
decode of very wide input functions.

The XC5200 CLB consists of four LCs, as shown in
Figure 3. Each CLB has 20 independent inputs and 12
independent outputs. The top and bottom pairs of LCs can
be configured to implement 5-input functions. The
challenge of FPGA implementation software has always
been to maximize the usage of logic resources. The
XC5200 family addresses this issue by surrounding each
CLB with two types of local interconnect -- the LIM and
direct connects. These two interconnect resources,
combined with the CLB, form the VersaBlock, represented
in Figure 4.

Figure 2.

XC5200 Logic Cell (Four LCs per CLB)

X4956

CE CK

CLR

XC5200 Logic Cell Array Family

Preliminary (v1.0)

Figure 3.

Configurable Logic Block

X4957

LC3

LC2

LC1

LC0

CE CK

CLR

LC0

Figure 4.

VersaBlock

The LIM provides 100% connectivity of the inputs and
outputs of each LC in a given CLB. The benefit of the LIM
is that no general routing resources are required to
connect feedback paths within a CLB. The LIM connects
to the GRM via 24 bidirectional nodes.

The direct connects allow immediate connections to
neighboring CLBs, once again without using any of the
general interconnect. These two layers of local routing
resource improve the granularity of the architecture,
effectively making the XC5200 family a "sea of logic cells."
Each VersaBlock has four 3-state buffers that share a
common enable line and directly drive horizontal
Longlines, creating robust on-chip bussing capability. The
VersaBlock allows fast, local implementation of logic
functions, effectively implementing user designs in a
hierarchical fashion. These resources also minimize local
routing congestion and improve the efficiency of the
general interconnect, which is used for connecting larger
groups of logic. It is this combination of both fine-grain and
coarse-grain architecture attributes that maximize logic
utilization in the XC5200 family. This symmetrical structure
takes full advantage of the third metal layer, freeing the
placement software to pack user logic optimally with
minimal routing restrictions.

X5707

CLB

Direct Connects

GRM

LIM

LC3

LC2

LC1

LC0

VersaRing I/O Interface

The interface between the IOBs and core logic has been
redesigned in the XC5200 family. The IOBs are
completely decoupled from the core logic. The XC5200
IOBs contain dedicated boundary-scan logic for added
board-level testability, but do not include input or output
registers. This approach allows a maximum number of
IOBs to be placed around the device, improving the I/O-to-
gate ratio and decreasing the cost per I/O. A "freeway" of
interconnect cells surrounding the device forms the
VersaRing, which provides connections from the IOBs to
the internal logic These incremental routing resources
provide abundant connections from each IOB to the
nearest VersaBlock, in addition to Longline connections
surrounding the device. The VersaRing eliminates the
historic trade-off between high logic utilization and pin
placement flexibility. These incremental edge resources
give users increased flexibility in preassigning (i.e.,
locking) I/O pins before completing their logic designs.
This ability accelerates time-to-market, since PCBs and
other system components can be manufactured
concurrent with the logic design.

General Routing Matrix

The GRM is functionally similar to the switch matrices
found in other architectures, but it is novel in its tight
coupling to the logic resources contained in the
VersaBlocks. Advanced simulation tools were used during
the development of the XC5200 architecture to determine
the optimal level of routing resources required. The
XC5200 family contains six levels of interconnect
hierarchy -- a series of single-length lines, double-length
lines, and Longlines all routed through the GRM. The
direct connects, LIM, and logic-cell feedthrough are

contained within each VersaBlock. Throughout the
XC5200 interconnect, an efficient multiplexing scheme, in
combination with TLM, was used to improve the overall
efficiency of silicon usage.

Performance Overview

The XC5200 family has been benchmarked with many
designs running synchronous clock rates up to 40 MHz. The
performance of any design depends on the circuit to be
implemented, and the delay through the combinatorial and
sequential logic elements, plus the delay in the interconnect
routing. Table 4 shows some performance numbers for
representative circuits, using worst-case timing parameters
for the Engineering Sample (ES) speed grade. A rough
estimate of timing can be made by assuming 6 ns per logic
level, which includes direct-connect routing delays. More
accurate estimations can be made using the information in
the Switching Characteristic Guideline section.

Table 4.

Performance for Several Common Circuit Functions

Function

XC5200 Speed Grade

-6

-5

-4

16-bit Decoder from Input Pad

9 ns

8 ns

24-bit Accumulator

32 MHz

39 MHz

16-to-1 Multiplexer

16 ns

13 ns

16-bit Unidirectional Loadable Counter

40 MHz

50 MHz

16-bit U/D Counter

40 MHz

50 MHz

16-bit Adder

24 ns

20 ns

24-bit Loadable U/D Counter

36 MHz

42 MHz

XC5200 Logic Cell Array Family

Preliminary (v1.0)

Development System

The powerful features of the XC5200 device family require
an equally powerful, yet easy-to-use, set of development
tools. Xilinx provides an enhanced version of the Xilinx
Automatic CAE Tools (XACT), optimized for the XC5200
family.

As with other logic technologies, the basic methodology
for XC5200 FPGA design consists of three interrelated
steps: design entry, implementation, and verification.
Popular generic tools are used for entry and simulation
(for example, Viewlogic Systems's Viewdraw schematic
editor and Viewsim simulator), but architecture-specific
tools are needed for implementation.

All Xilinx development system software is integrated under
the Xilinx Design Manager (XDMTM), providing designers
with a common user interface regardless of their choices
of entry and verification tools. XDM simplifies the selection
of command-line options with pull-down menus and online
help text. Application programs ranging from schematic
capture to Partitioning, Placement, and Routing (PPR)
can be accessed from XDM, while the program-command
sequence is generated and stored for documentation prior
to execution. The XMAKE command, a design compilation
utility, automates the entire implementation process,
automatically retrieving the design's input files and
performing all the steps needed to create configuration
and report files.

Several advanced features of the XACT system facilitate
XC5200 FPGA design. RPMs -- schematic-based macros
with relative location constraints to guide their placement
within the FPGA -- help to ensure an optimized
implementation for common logic functions. An
abundance of local routing permits RPMs to be contained
within a single VersaBlock or to span across multiple
VersaBlocks. XACT-Performance allows designers to
enter the exact performance requirements during design
entry, at the schematic level, to guide PPR.

Design Entry

Designs can be entered graphically, using schematic-
capture software, or in any of several text-based formats
(such as Boolean equations, state-machine descriptions,
and high-level design languages).

Xilinx and third-party CAE vendors have developed library
and interface products compatible with a wide variety of
design-entry and simulation environments. A standard
interface-file specification, Xilinx Netlist File (XNF), is
provided to simplify file transfers into and out of the XACT
development system.

Xilinx offers XACT development system interfaces to the
following design environments:

· Viewlogic Systems (Viewdraw, Viewsim)

· Mentor Graphics V8 (NETED, QuickSim, Design

Architect, QuickSim II)

· OrCAD (SDT, VST)

· Synopsys (Design Compiler, FPGA Compiler)

· Xilinx-ABEL (State Machine module generator)

· X-BLOX (Graphical Mode Generator)

Many other environments are supported by third-party
vendors. Currently, more than 100 packages are
supported.

The unified schematic library for the XC5200 FPGA
reflects the wide variety of logic functions that can be
implemented in these versatile devices. The library
contains over 400 primitives and macros, ranging from 2-
input AND gates to 16-bit accumulators, and includes
arithmetic functions, comparators, counters, data
registers, decoders, encoders, I/O functions, latches,
Boolean functions, multiplexers, shift registers, and barrel
shifters.

Designing with macros is as easy as designing with
standard SSI/MSI functions. The "soft macro" library
contains detailed descriptions of common logic functions,
but does not contain any partitioning or routing
information. The performance of these macros depends,
therefore, on how the PPR software processes the design.
RPMs, on the other hand, do contain predetermined
partitioning and relative placement information, resulting
in an optimized implementation for these functions. Users
can create their own library elements -- either soft macros
or RPMs -- based on the macros and primitives of the
standard library.

The X-BLOX design language is a graphics-based high-
level description language (HDL) that allows designers to
use a schematic editor to enter designs as a set of generic
modules. The X-BLOX compiler synthesizes and
optimizes the modules for the target device architecture,
automatically choosing the appropriate architectural
resources for each function.

The XACT design environment supports hierarchical
design entry, with top-level drawings defining the major
functional blocks, and lower-level descriptions defining the
logic in each block. The implementation tools
automatically combine the hierarchical elements of a
design. Different hierarchical elements can be specified
with different design entry tools, allowing the use of the
most convenient entry method for each portion of the
design.

Design Implementation

The design implementation tools satisfy the requirements
for an automated design process. Logic partitioning, block
placement, and signal routing are performed by the PPR
program. The partitioner takes the logic from the entered
design and maps the logic into the architectural resources
of the FPGA (such as the logic blocks, I/O blocks, and 3-
state buffers). The placer then determines the best
locations for the blocks, depending on their connectivity
and the required performance. The router finally connects
the placed blocks together.

The PPR algorithms support fully automatic
implementation of most designs. However, for demanding
applications, the user may exercise various degrees of
control over the automated implementation process.
Optionally, user-designated partitioning, placement, and
routing information can be specified as part of the design-
entry process. The implementation of highly structured
designs can benefit greatly from the basic floorplanning
techniques familiar to designers of large gate arrays.

The PPR program includes XACT-Performance, a feature
that allows designers to specify the timing requirements
along entire paths during design entry. Timing path
analysis routines in PPR then recognize and
accommodate the user-specified requirements. Timing
requirements can be entered on the schematic in a form
directly relating to the system requirements (such as the
targeted minimum clock frequency, or the maximum
allowable delay on the data path between two registers).
So, while the timing of each individual net is not
predictable, the overall performance of the system along
entire signal paths is automatically tailored to match user-
generated specifications.

Design Verification

The high development cost associated with common
mask-programmed gate arrays necessitates extensive
simulation to verify a design. Due to the custom nature of
masked gate arrays, mistakes or last-minute design
changes cannot be tolerated. A gate-array designer must
simulate and test all logic using simulation software.
Simulation describes what happens in a system under
worst-case situations. However, simulation can be tedious
and slow, and simulation vectors must be generated. A
few seconds of system time can take weeks to simulate.

Programmable-gate-array users, however, can use in-
circuit debugging techniques in addition to simulation.
Because Xilinx devices are reprogrammable, designs can
be verified in real time without the need for extensive
simulation vectors.

The XACT development system supports both simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from
the design database. This data can then be sent to the
simulator to verify timing-critical portions of the design
database using XDELAY, the Xilinx static timing analyzer
tool. Back-annotation -- the process of mapping the
timing information back into the signal names and
symbols of the schematic -- eases the debugging effort.

For in-circuit debugging, the XACT development system
includes a serial download and readback cable
(XChecker) that connects the FPGA in the system to the
PC or workstation through an RS232 serial port. The
engineer can download a design or a design revision into
the system for testing. The designer can also single-step
the logic, read the contents of the numerous flip-flops on
the device, and observe internal logic levels. Simple
modifications can be downloaded into the system in a
matter of minutes.

XC5200 Logic Cell Array Family

Preliminary (v1.0)

Figure 5.

Two LUTs in Parallel Combined to Create a 5-input Function

out

Qout

CLR

LC0

5-Input Function

F5_MUX

F4
F3
F2
F1

I1
I2
I3
I4

LC1

X5710

Detailed Functional Description

CLB Logic

Figure 3 shows the logic in the XC5200 CLB, which
consists of four Logic Cells (LC[3:0]). Each Logic Cell
consists of an independent 4-input Lookup Table (LUT),
and a D-Type flip-flop or latch with common clock, clock
enable, and clear, but individually selectable clock polarity.
Additional logic features provided in the CLB are:

· High-speed carry propagate logic.

· High-speed pattern decoding.

· High-speed direct connection to flip-flop D-inputs.

· Each flip-flop can be programmed individually as either

a transparent, level-sensitive latch or a D flip-flop.

· Four 3-state buffers with a shared Output Enable.

· Two 4-input LUTs can be combined to form an

independent 5-input LUT.

5-Input Functions

Figure 5 illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.

Carry Function

The XC5200 family supports a carry-logic feature that
enhances the performance of arithmetic functions such as
counters, adders, etc. A carry multiplexer (CY_MUX)
symbol on a schematic is used to indicate the XC5200
carry logic. This symbol represents the dedicated 2:1
multiplexer in each LC that performs the one-bit high-
speed carry propagate per logic cell (four bits per CLB).

While the carry propagate is performed inside the LC, an
adjacent LC must be used to complete the arithmetic
function. Figure 6 represents an example of an adder
function. The carry propagate is performed on the CLB

shown, which also generates the half-sum for the four-bit
adder. An adjacent CLB is responsible for XORing the
half-sum with the corresponding carry-out. Thus an adder
or counter requires two LCs per bit. Notice that the carry
chain requires an initialization stage, which the XC5200
family accomplishes using the carry initialize (CY_INIT)
macro and one additional LC.

The XC5200 library contains a set of RPMs and arithmetic
functions designed to take advantage of the dedicated
carry logic. Using and modifying these macros makes it
much easier to implement customized RPMs, freeing the
designer from the need to become an expert on
architectures.

Figure 6.

XC5200 CY_MUX Used for Adder Carry Propagate

XOR

F=0

carry out

carry3

LC3

LC2

carry in

CY_MUX

LC1

LC0

CLR

half sum0

carry0

half sum2

half sum1

carry1

carry2

half sum3

A3
or
B3

A3 and B3
to any two

A2 and B2
to any two

A2
or
B2

A1
or
B1

A1 and B1
to any two

A0
or
B0

A0 and B0
to any two

XOR

LC3

LC2

LC1

LC0

CLR

sum0

sum2

sum1

sum3

Initialization of
carry chain (One Logic Cell)

X5709

XC5200 Logic Cell Array Family

Preliminary (v1.0)

Figure 7.

XC5200 CY_MUX Used for Decoder Cascade Logic

F4
F3
F2
F1

A15

A14

A13

A12

A11

A10

AND

F=0

cascade out

out

LC3

LC2

cascade in

CY_MUX

LC1

Initialization of
carry chain (One Logic Cell)

LC0

CLR

AND

X5708

Cascade Function

Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4-input function generators can be
configured to take advantage of these four cascaded

CY_MUXes. Note that AND and OR cascading are
specific cases of a general decode. In AND cascading all
bits are decoded equal to logic one, while in OR
cascading all bits are decoded equal to logic zero. The
flexibility of the LUT achieves this result.

3-State Buffers

The XC5200 family has four dedicated TBUFs per CLB.
The four buffers are individually configurable through four
configuration bits to operate as simple non-inverting
buffers or in 3-state mode. When in 3-state mode the
CLB's output enable (TS) control signal drives the enable
to all four buffers (see Figure 8). Each TBUF can drive up
to two horizontal Longlines

Oscillator

The XC5200 oscillator (OSC52) divides the internal 16-
MHz clock or a user clock that is connected to the "C" pin.
The user then has the choice of dividing by 4, 16, 64, or
256 for the "OSC1" output and dividing by 2, 8, 32, 128,
1024, 4096, 16384, or 65536 for the "OSC2" output. The
division is specified via a "DIVIDEn_BY=x" attribute on the
symbol, where n=1 for OSC1, or n=2 for OSC2. The
OSC5 macro is used where an internal oscillator is
required. The CK_DIV macro is applicable when a user
clock input is specified (see Figure 9).

Figure 8.

XC5200 3-State Buffer

Figure 9.

XC5200 Oscillator Macros

CLB

LC3

LC2

LC1

LC0

CLB

Horizontal
Longlines

X5706

OSC5

OSC1

OSC2

CK_DIV

OSC1

OSC2

CLK

Start-Up

On start-up, all XC5200 internal flip-flops are reset. The
XC5200 devices do not support the "INIT=" attribute.
Thus, the XC5200 family has only a global reset (GR)
signal. The user can assign the pin location for the GR
signal and use it to reset asynchronously all of the flip-
flops in the design without using general routing
resources. The user can also assign a positive or negative
polarity to GR.

Boundary Scan

XC5200 devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that
implement the EXTEST, SAMPLE/PRELOAD, and
BYPASS instructions. The TAP can also support two
USERCODE instructions.

Boundary-scan operation is independent of individual IOB
configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
unbonded IOBs. Retaining the bidirectional test capability
after configuration provides flexibility for interconnect
testing.

Also, internal signals can be captured during EXTEST by
connecting them to unbonded IOBs, or to the unused
outputs in IOBs used as unidirectional input pins. This
technique partially compensates for the lack of INTEST
support.

The public boundary-scan instructions are always
available prior to configuration. After configuration, the
public instructions and any USERCODE instructions are
only available if specified in the design. While SAMPLE
and BYPASS are available during configuration, it is
recommended that boundary-scan operations not be
performed during this transitory period.

In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
Logic Cell Array (LCATM) device, and to read back the
configuration data.

All of the XC4000 boundary-scan modes are supported in
the XC5200 family. Three additional outputs for the User
Register are provided (Reset, Update, and Shift),
representing the decoding of the corresponding state of
the boundary-scan internal state machine. For details on
boundary scan, refer to "Boundary Scan in XC4000
Devices -- Application Note" on pages 8-45 through 8-42
of the 1994 Xilinx Programmable Logic Data Book.

XC5200 Logic Cell Array Family

Preliminary (v1.0)

VersaBlock Routing

Local Interconnect Matrix

The GRM connects to the VersaBlock via 24 bidirectional
ports (M0-M23). Excluding direct connections, global nets,
and 3-statable Longlines, all VersaBlock inputs and
outputs connect to the GRM via these 24 ports. Four 3-
statable unidirectional signals (TQ0-TQ3) drive out of the
VersaBlock directly onto the horizontal Longlines. Two
horizontal global nets (GH0 and GH1) and two vertical
global nets (GV0 and GV1) connect directly to every CLB
clock pin; they can connect to other CLB inputs via the
GRM. Each CLB also has four unidirectional direct
connects to each of its four neighboring CLBs. These
direct connects can also feed directly back to the CLB
(see Figure 10).

In addition, each CLB has 16 direct inputs, four direct
connections from each of the neighboring CLBs. These
direct connections provide high-speed local routing that
bypasses the GRM.

The 13 CLB outputs (12 LC outputs plus a V

/GND

signal) connect to the eight VersaBlock outputs via the
output multiplexers, which consist of eight fully populated
13-to-1 multiplexers. Of the eight VersaBlock outputs, four
signals drive each neighboring CLB directly, and provide a
direct feedback path to the input multiplexers. The four
remaining multiplexer outputs can drive the GRM through
four TBUFs (TQ0-TQ3). All eight multiplexer outputs can
connect to the GRM through the bidirectional M0-M23
signals. All eight signals also connect to the input
multiplexers and are potential inputs to that CLB.

CLB inputs have several possible sources: the 24 signals
from the GRM, 16 direct connections from neighboring
VersaBlocks, four signals from global, low-skew buffers
(GH0, GH1, GV0, and GV1), and the four signals from the
CLB output multiplexers. Unlike the output multiplexers,
the input multiplexers are not fully populated; i.e., only a
subset of the available signals can be connected to a
given CLB input. The flexibility of LUT input swapping and
LUT mapping compensates for this limitation. For
example, if a 2-input NAND gate is required, it can be
mapped into any of the four LUTs, and use any two of the
four inputs to the LUT.

Direct Connects

The unidirectional direct-connect segments are connected
to the logic input/output pins through the CLB's input and
output multiplexer array, and thus bypass the
programmable routing matrix altogether. These lines are
intended to increase the routing channel utilization where
possible, while simultaneously reducing the delay incurred
in speed-critical connections.

The direct connects also provide a high-speed path from
the edge CLBs to the VersaRing input/output buffers, and
thus reduce set-up time, clock-to-out, and combinational
propagation delay.

The direct connects are ideal for developing customized
RPM cells. Using direct connects improves the macro
performance, and leaves the other routing channels intact
for improved routing. Direct connects can also route
through a CLB using one of the four cell-feedthrough
paths.

XC5200 Logic Cell Array Family

Preliminary (v1.0)

General Routing Matrix

The General Routing Matrix, shown in Figure 11, provides
flexible bidirectional connections to the Local Interconnect
Matrix through a hierarchy of different-length metal
segments in both the horizontal and vertical directions. A
programmable interconnect point (PIP) establishes an
electrical connection between two wire segments. The
PIP, consisting of a pass transistor switch controlled by a
memory element, provides bidirectional (in some cases,
unidirectional) connection between two adjoining wires. A
collection of PIPs inside the General Routing Matrix and in
the Local Interconnect Matrix provides connectivity
between various types of metal segments. A hierarchy of
PIPs and associated routing segments combine to provide
a powerful interconnect hierarchy:

· Forty bidirectional single-length segments per CLB

provide ten routing channels to each of the four
neighboring CLBs in four directions.

· Sixteen bidirectional double-length segments per CLB

provide four routing channels to each of four other (non-
neighboring) CLBs in four directions.

· Eight horizontal and eight vertical bidirectional Longline

segments span the width and height of the chip,
respectively.

· Two low-skew horizontal and vertical unidirectional

global-line segments span each row and column of the
chip, respectively.

Single- and Double-Length Lines

The single- and double-length bidirectional line segments
make up the bulk of the routing channels. The double-
length lines hop across every other CLB to reduce the
propagation delays in speed-critical nets. Regenerating
the signal strength is recommended after traversing three
or four such segments. XACT place-and-route software
automatically connects buffers in the path of the signal as
necessary. Single- and double-length lines cannot drive
onto Longlines and global lines; Longlines and global lines
can, however, drive onto single- and double-length lines.
As a general rule, Longline and global-line connections to
the programmable routing matrix are unidirectional, with
the signal direction from these lines toward the routing
matrix.

Longlines

Longlines are used for high-fan-out signals, 3-state
busses, low-skew nets, and faraway destinations. Row
and column splitter PIPs in the middle of the array
effectively double the total number of Longlines by
electrically dividing them into two separated half-lines. The
horizontal Longlines are driven by the 3-state buffers in

each CLB, and are driven by similar buffers at the
periphery of the array from the VersaRing I/O Interface.

Bus-oriented microprocessor designs are accommodated
by using horizontal Longlines in conjunction with the 3-
state buffers in the CLB and in the VersaRing. Additionally,
programmable keeper cells at the periphery can be
enabled to retain the last valid logic level on the Longlines
when all buffers are in 3-state mode.

Longlines connect to the single-length or double-length
lines, or to the logic inside the CLB, through the General
Routing Matrix. The only manner in which a Longline can
be driven is through the four 3-state buffers; therefore, a
Longline-to-Longline or single-line-to-Longline connection
through PIPs in the General Routing Matrix is not
possible. Again, as a general rule, long- and global-line
connections to the General Routing Matrix are
unidirectional, with the signal direction from these lines
toward the routing matrix.

The XC5200 family has no pull-ups on the ends of the
Longlines sourced by TBUFs. Consequently, wired
functions (i.e., WAND and WORAND) and wide
multiplexing functions requiring pull-ups for undefined
states (i.e., bus applications) must be implemented in a
different way. In the case of the wired functions, the same
functionality can be achieved by taking advantage of the
carry/cascade logic described above, implementing a
wide logic function in place of the wired function. In the
case of 3-state bus applications, the user must insure that
all states of the multiplexing function are defined. This
process is as simple as adding an additional TBUF to
drive the bus High when the previously undefined states
are activated.

Global Clock Buffers

Global buffers in Xilinx FPGAs are special buffers that
drive a dedicated routing network called Global Lines, as
shown in Figure 12. This network is intended for high-fan-
out clocks or other control signals, to maximize speed and
minimize skewing while distributing the signal to many
loads.

The XC5200 family has a total of four global buffers
(BUFG symbol in the library), each with its own dedicated
routing channel. Two are distributed vertically and two
horizontally throughout the LCA.

XC5200 Logic Cell Array Family

Preliminary

Global Lines

Two pairs of horizontal and vertical global lines provide
low-skew clock signals to the CLBs. Global lines are
driven by low-skew buffers inside the VersaRing. The
global lines provide direct input only to the CLB clock pins.
The global lines also connect to the General Routing
Matrix to provide access from these lines to the function
generators and other control signals.

Four clock input pads at the corners of the chip, as shown
in Figure 12, provide a high-speed, low-skew clock
network to each of the four global-line buffers. In addition
to the dedicated pad, the global lines can be sourced by
internal logic. PIPs from several routing channels within
the VersaRing, inside the IOI cell, can also be configured
to drive the global-line buffers.

VersaRing Input/Output Interface

The VersaRing, shown in Figure 13, is positioned between
the core logic and the pad ring; it has all the routing
resources of a VersaBlock without the CLB logic. The
VersaRing decouples the pad ring's pitch from the core's
pitch. Each VersaRing Cell provides up to four pad-cell
connections on one side, and connects directly to the CLB
ports on the other side. Depending on placement and pad-
cell pitch, any number of pad cells to a maximum of four
can be connected to a VersaRing cell. Note: there are no
direct connects from the Pads on top and bottom edges.

Input/Output Pad

The I/O pad, shown in Figure 14, consists of an input buffer
and an output buffer. The output driver is an 8-mA full-rail
CMOS buffer with 3-state control. Two slew-rate control
modes are supported to minimize bus transients. Both the
output buffer and the 3-state control are invertible.

Figure 12. Global Lines

GCK1

GCK4

GCK3

GCK2

X5704

The input buffer has globally selected CMOS and TTL
input thresholds. The input buffer is invertible and also
provides a programmable delay line to assure reliable
chip-to-chip set-up and hold times. Minimum ESD
protection is 5 KV using the Human Body Model.

Figure 13. VersaRing I/O Interface

Figure 14. XC5200 I/O Block

GRM

VersaBlock

VersaRing

GRM

VersaBlock

Interconnect

Pad

X5705

PAD

Vcc

X4964

Table 5.

Configuration Modes

Mode

CCLK

Data

Master Serial

output

Bit-Serial

Slave Serial

input

Bit-Serial

Master Parallel up

output

Byte-Wide, 00000

Master Parallel down

output

Byte-Wide, 3FFFF

Peripheral Synchronous *

input

Byte-Wide

Peripheral Asynchronous

output

Byte-Wide

Express

input

Byte-Wide

Reserved

* Peripheral Synchronous can be considered byte-wide Slave Parallel

Configuration

Configuration is the process of loading design-specific
programming data into one or more LCA devices to define
the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the
command registers of a programmable peripheral chip.
Each configuration bit defines the state of a static memory
cell that controls either a function LUT bit, a multiplexer
input, or an interconnect pass transistor. The XACT
development system translates the design into a netlist
file. It automatically partitions, places, and routes the logic
and generates the configuration data in PROM format.

Modes

The XC5200 family has seven modes of configuration,
selected by a 3-bit input code applied to the LCA mode
pins (M0, M1, and M2). There are three self-clocking
Master modes, two Peripheral modes, a Slave serial
mode, and a new high-speed Slave parallel mode called
the Express. See Table 5.

Brief descriptions of the seven modes are provided below.
For details on all modes except Express, see pages 2-32
through 2-41 of the 1994 Xilinx Programmable Logic Data
Book.

Master Modes
The Master modes use an internal oscillator to generate
CCLK for driving potential slave devices, and to generate
address and timing for external PROM(s) containing the
configuration data. Master Parallel (up or down) modes
generate the CCLK signal and PROM addresses, and
receive byte parallel data, which is internally serialized

into the LCA data-frame format. The up and down
selection generates starting addresses at either zero or
3FFFF, to be compatible with different microprocessor
addressing conventions. The Master Serial Mode
generates CCLK and receives the configuration data in
serial form from configuration data in serial form from a
Xilinx serial-configuration PROM.

Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A READY/BUSY status is available as a handshake
signal. In the asynchronous mode, the internal oscillator
generates a CCLK burst signal that serializes the byte-
wide data. In the synchronous mode, an externally
supplied clock input to CCLK serializes the data.

Slave Serial Mode
In the Slave Serial mode, the LCA device receives serial-
configuration data on the rising edge of CCLK and, after
loading its configuration, passes additional data out,
resynchronized on the next falling edge of CCLK. Multiple
slave devices with identical configurations can be wired
with parallel DIN inputs so that the devices can be
configured simultaneously.

Daisy Chaining
Multiple devices may be daisy-chained together so that
they may be programmed using a single bitstream. The
first device in the chain may be set to operate in any
mode. All devices except the first device in the chain must
be set to operate in Slave Serial mode.

All CCLK pins are tied together and the data chain passes
from DOUT to DIN of successive devices along the chain.

XC5200 Logic Cell Array Family

Preliminary

Express Mode
The Express mode (see Figure 15) is similar to the Slave
serial mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An
external source is used to drive CCLK while byte-wide
data is loaded directly into the configuration data shift
registers. In this mode the XC5200 family is capable of
supporting a CCLK frequency of 10 MHz, which is
equivalent to an 80-MHz serial rate, because eight bits of
configuration data are being loaded per CCLK cycle. An
XC5210 in the Express mode, for instance, can be
configured in about 2 ms. The Express mode does not
support CRC error checking, but does support constant-
field error checking.

In the Express configuration mode, an external signal
drives the CCLK input(s) of the LCA device(s). The first
bytes of parallel configuration data must be available at
the D inputs of the LCA devices a short set-up time before
each rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge. See
Figure 16.

The Express mode is only supported by the XC5200
family. It may not be used, therefore, when an XC5200

device is daisy-chained with devices from other Xilinx
families.

If the first device is configured in the Express mode,
additional devices may be daisy-chained only if every
device in the chain is also configured in the Express
mode. CCLK pins are tied together and D7-D0 pins are
tied together for all devices along the chain. A status
signal is passed from DOUT to CS1 of successive devices
along the chain. The lead device in the chain has its CS1
input tied High (or floating, since there is an internal pull-
up). All devices receive and recognize the preamble and
length count, but frame data is accepted only when CS1 is
High and the device's configuration memory is not already
full. The status pin DOUT is pulled LOW two internal-
oscillator cycles (nominally 1 MHz per cycle) after INIT is
recognized as High, and remains Low until the device's
configuration memory is full. Then DOUT is pulled High to
signal the next device in the chain to accept the
configuration data on the D7-D0 bus.

How to Delay Configuration After Power-Up

For details on how to delay configuration after power-up,
refer to page 2-32 of the 1994 Xilinx Programmable Logic
Data Book.

Figure 15. Express Mode

INIT

CCLK

XC5200

CS1

D0-D7

DATA BUS

PROGRAM

INIT

CCLK

PROGRAM

INIT

DOUT

To Additional
Optional
Daisy-Chained
Devices

Optional

Daisy-Chained

XC5200

+5V

CS1

D0-D7

PROGRAM

X6153

Figure 16. Express Mode Programming Switching Characteristics

X6154

BYTE

CCLK

LCA Filled

INIT

D0-D7

Serial Data Out

(DOUT)

RDY/BUSY

CS1

BYTE

Internal INIT

Description

Symbol

Min

Max

Units

CCLK

INIT (High) Setup time required

DIN Setup time required

DIN Hold time required

CCLK High time

CCH

CCLK Low time

CCL

CCLK Frequency

MHz

Preliminary

Format

Table 6 describes the XC5200 configuration data stream.
Table 7 provides details of the internal configuration data
structure.

Configuration Sequence

Figure 17 illustrates the XC5200 start-up sequence. It is
described in detail in the sections below.

Clear Internal Logic
When reprogramming the XC5200 chip, a contention-free
state must be reached before memory initialization can
begin. In this state internal control lines sequence
activities in the following order: long lines are disabled,
output drivers are forced Low, and interconnect lines are
discharged. Each of these operations requires one cycle
of the 1-MHz Initialization clock. This sequencing is
important only when reprogramming, because the
contention-free state is immediately entered when
configuring from a power-on state.

XC5200 Logic Cell Array Family

Preliminary

Table 6.

Unified XC5200 Bitstream Format

Data Type

Value

Fill Byte

11111111

Preamble

11110010

Length Counter

COUNT(23:0)

Fill Byte

11111111

Start Byte

11111110

Data Frame *

DATA(N-1:0)

Cyclic Redundancy Check or
Constant Field Check

CRC(3:0) or
0110

Fill Nibble

1111

Extend Write Cycle

FFFFFF

Postamble

11111110

Fill Bytes (30)

FFFF...FF

Legend:

(unshaded)

Only once per bitstream

(light)

Once per data frame

(dark)

Once per device

Table 7.

Internal Configuration Data Structure

Device

VersaBlock

Array

PROM

Size

(bits)

Xilinx

Serial Prom

Needed

XC5202

8 x 8

42,448

XC1765

XC5204

10 x 12

70,736

XC1728

XC5206

14 x 14

106,320

XC17128

XC5210

18 x 18

165,520

XC17256

XC5215

22 x 22

237,776

XC17256

Bits per Frame = (34 x number of Rows) + 28 for the
top + 28 for the bottom + 4 splitter bits + 8 start bits + 8
error check bits + 4 fill bits + 4 extended write bits

Number of Frames = (12 x number of Columns) + 7 for
the left edge + 8 for the right edge + 1 splitter bit

Program Data = (Bits per Frame x Number of Frames)
+ 48 header bits + 8 postamble bits + 280 fill bits

PROM Size = Program Data

Figure 17. Start-up Sequence

INIT

High? if

Master

Sample

Mode Lines

Load One

Configuration

Data Frame

Frame

Error

Pass

Configuration

Data to DOUT

VCC

Yes

Operational

Start-Up

Sequence

Yes

~1.3

s per Frame

Master CCLK

Goes Active after

50 to 250

Pull INIT Low

and Stop

X6037

EXTEST*

SAMPLE/PRELOAD*

BYPASS

CONFIGURE*

(*only when PROGRAM = High)

SAMPLE/PRELOAD

BYPASS

EXTEST

SAMPLE PRELOAD

BYPASS

USER 1
USER 2

CONFIGURE

READBACK

If Boundary Scan
is Selected

Config-

uration

memory

Full

CCLK

Count Equals

Length

Count

Completely Clear

Configuration

Memory

LDC Output = L, HDC Output = H

Boundary Scan

Instructions

Available:

I/O Active

Generate

One Time-Out Pulse

of 4 ms

PROGRAM

= Low

Yes

Clear Address Registers
During this phase the configuration address registers are
cleared to ensure that they will contain at most a single
token at all times. Prior to memory initialization, the
XC5200 device eliminates the possibility of multiple
tokens within the address register, as is typically the case
when powering on.

Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When V

reaches the voltage at which

portions of the LCA begin to operate (i.e., performs a
write-and-read test of a sample pair of configuration
memory bits), the programmable I/O buffers are 3-stated
with active high-impedance pull-up resistors. A time-out
delay -- nominally 4 ms -- is initiated to allow the power-
supply voltage to stabilize. For correct operation the
power supply must reach V

(min) by the end of the time-

out, and must not dip below it thereafter.

There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have
completed initialization. Since XC2000 devices do not
have this signal, extra care must be taken to guarantee
proper operation when daisy-chaining them with XC5200
devices. For proper operation with XC3000 devices, the
RESET signal, which is used in XC3000 to delay
configuration, should be connected to INIT.

If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.

During all three phases -- Power-on, Initialization, and
Configuration -- DONE is held Low; HDC, LDC, and INIT
are active; DOUT is driven; and all I/O buffers are
disabled.

Initialization
This phase clears the configuration memory and
establishes the configuration mode.

The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An open-
drain bidirectional signal, INIT, is released when the
configuration memory is completely cleared. The device
then tests for the absence of an external active-low level
on INIT. The mode lines are sampled two internal clock
cycles later (nominally 2

s).

The master device waits an additional 32

s to 256

(nominally 64-128

s) to provide adequate time for all of

the slave devices to recognize the release of INIT as well.
Then the master device enters the Configuration phase.

Configuration
The length counter begins counting immediately upon
entry into the configuration state. In slave-mode operation
it is important to wait at least two cycles of the internal
1-MHz clock oscillator after INIT is recognized before
toggling CCLK and feeding the serial bitstream.
Configuration will not begin until the internal configuration
logic reset is released, which happens two cycles after
INIT goes High. A master device's configuration is
delayed from 32 to 256

s to ensure proper operation with

any slave devices driven by the master device.

A preamble field at the beginning of the configuration data
stream indicates that the next 24 bits represent the length
count. The length count equals the total number of
configuration bits needed to load the complete
configuration data to all daisy-chained devices. Once the
preamble and length-count values have been passed
through to the next device in the daisy-chain, DOUT is
held High to prevent start bits from reaching any daisy-
chained devices. After fully configuring itself, the device
passes serial data to downstream daisy-chained devices
via DOUT until the full length count is reached.

Errors in the configuration bitstream are checked at the
end of a frame of data. The device does not check the
preamble or length count for errors. In a daisy-chained
configuration, configuration data for downstream devices
are not checked for errors. If an error is detected after
reading a frame, the ERR pin (also known as INIT) is
immediately pulled Low and all configuration activity
ceases. However, a master or Peripheral Asynchronous
device will continue outputting a configuration clock and
incrementing the PROM address indefinitely even though
it will never complete configuration. A reprogram or
power-on must be applied to remove the device from this
state.

Start-Up and Operation
The XC5200 start-up sequence is identical to that of the
XC4000 family. Each of these events may occur in any
order: (a) DONE is pulled High; and/or (b) user I/Os
become active; and/or (c) Internal Reset is deactivated.
As a configuration option, the three events may be
triggered by a user clock rather than by CCLK, or the start-
up sequence may be delayed by externally holding the
DONE pin Low.

In any mode, the clock cycles of the start-up sequence
hare not included in the length count. The length of the
bitstream is greater than the length count.

XC5200 Logic Cell Array Family

Preliminary

Pin Functions During Configuration

Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a

50-k

to 100-k

pull-up resistor.

CONFIGURATION MODE:

<M2:M1:M0>

USER

OPERATION

SLAVE

<1:1:1>

MASTER-SER

<0:0:0>

SYN.PERIPH

<0:1:1>

ASYN.PERIPH

<1:0:1>

MASTER-HIGH

<1:1:0>

MASTER-LOW

<1:0:0>

A16

GCK1-I/O

A17

I/O

TDI

TDI-I/O

TCK

TCK-I/O

TMS

TMS-I/O

I/O

M1 (HIGH) (I)

M1 (LOW) (I)

M1 (HIGH) (I)

M1 (LOW) (I)

M1 (HIGH) (I)

M1 (LOW) (I)

I/O

M0 (HIGH) (I)

M0 (LOW) (I)

M0 (HIGH) (I)

M0 (LOW) (I)

I/O

M2 (HIGH) (I)

M2 (LOW) (I)

M2 (HIGH) (I)

I/O

GCK2-I/O

HDC (HIGH)

I/O

LDC (LOW)

I/O

INIT-ERROR

I/O
I/O

DONE

PROGRAM (I)

PROGRAM

DATA 7 (I)

I/O

GCK3-I/O

DATA 6 (I)

I/O

DATA 5 (I)

I/O

CSO (I)

I/O

DATA 4 (I)

I/O

DATA 3 (I)

I/O

RS (I)

I/O

DATA 2 (I)

I/O

DATA 1 (I)

I/O

RDY/BUSY

RCLK

I/O

DIN (I)

DATA 0 (I)

I/O

DOUT

I/O

CCLK (I)

CCLK (O)

CCLK (I)

CCLK (O)

CCLK (I)

TDO

TDO-I/O

WS (I)

I/O

GCK4-I/O

CS1 (I)

I/O

A10

I/O

A11

I/O

A12

I/O

A13

I/O

A14

I/O

A15

I/O

ALL OTHERS

Represents a 50-k

to 100-k

pull-up before and during configuration

* INIT is an open-drain output during configuration

(I) Represents an input

(O) Represents an output

Permanently Dedicated Pins

Eight or more (depending on package type) connections
to the nominal +5-V supply voltage. All must be
connected.

GND

Eight or more (depending on package type) connections
to ground. All must be connected.

CCLK

During configuration, Configuration Clock is an output of
the LCA in master modes or Asynchronous Peripheral
mode, but is an input to the LCA in Slave Serial mode and
Synchronous Peripheral mode.

After configuration, CCLK has a weak pull-up resistor and
can be selected as Readback Clock.

DONE

This is a bidirectional signal with optional pull-up resistor.

As an output, it indicates the completion of the
configuration process. The configuration program
determines the exact timing, the clock source for the Low-
to-High transition, and enable of the pull-up resistor.

As an input, a Low level on DONE can be configured to
delay the global logic initialization or the enabling of
outputs.

PROGRAM

This is an active-Low input, held Low during configuration,
that forces the LCA to clear its configuration memory.

When PROGRAM goes High, the LCA executes a
complete clear cycle, before it goes into a WAIT state and
releases INIT. After configuration, it has an optional pull-
up resistor.

User I/O Pins That Can Have Special Functions

RDY/BUSY

During peripheral modes, this pin indicates when it is
appropriate to write another byte of data into the LCA
device. The same status is also available on D7 in
Asynchronous Peripheral mode, if a read operation is
performed when the device is selected. After
configuration, this is a user-programmable I/O pin.

RCLK

During Master Parallel configuration, each change on the
A0-15 outputs is preceded by a rising edge on RCLK, a
redundant output signal. After configuration, this is a user-
programmable I/O pin.

M0, M1, M2

As mode inputs, these pins are sampled before the start of
configuration to determine the configuration mode to be
used.

After configuration, M0, M1, and M2 become user-
programmable I/O.

TDO

If boundary scan is used, this is the Test Data Output.

If boundary scan is not used, this pin becomes user-
programmable I/O.

TDI, TCK, TMS

If boundary scan is used, these pins are Test Data In, Test
Clock, and Test Mode Select inputs, respectively, coming
directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after
configuration is completed.

If the boundary scan option is not selected, all boundary
scan functions are inhibited once configuration is
completed. These pins become user-programmable I/O.

HDC

High During Configuration is driven High until
configuration is completed. It is available as a control
output indicating that configuration is not yet completed.
After configuration, this is a user-programmable I/O pin.

Pin Descriptions

XC5200 Logic Cell Array Family

Preliminary

LDC

Low During Configuration is driven Low until configuration
completes. It is available as a control output indicating that
configuration is not yet completed. After configuration, this
is a user-programmable I/O pin.

INIT

Before and during configuration, this is a bidirectional
signal. An external pull-up resistor is recommended.

As an active-Low open-drain output, INIT is held Low
during the power stabilization and internal clearing of the
configuration memory. As an active-Low input, it can be
used to hold the LCA device in the internal WAIT state
before the start of configuration. Master-mode devices
stay in a WAIT state an additional 30 to 300

s after INIT

has gone High.

During configuration, a Low on this output indicates that a
configuration data error has occurred. After configuration,
this is a user-programmable I/O pin.

GCK1 - GCK4

Four Global Inputs each drive a dedicated internal global
net with short delay and minimal skew. If not used for this
purpose, any of these pins is a user-programmable I/O
pin.

CS0, CS1, WS, RS

These four inputs are used in peripheral modes. The chip
is selected when CS0 is Low and CS1 is High. While the
chip is selected, a Low on Write Strobe (WS) loads the
data present on the D0 - D7 inputs into the internal data
buffer; a Low on Read Strobe (RS) changes D7 into a
status output: High if Ready, Low if Busy, and D0...D6 are
active Low. WS and RS should be mutually exclusive, but
if both are Low simultaneously, the Write Strobe overrides.
After configuration, these are user-programmable I/O
pins.

A0 - A17

During Master Parallel mode, these 18 output pins
address the configuration EPROM. After configuration,
these are user-programmable I/O pins.

D0 - D7

During Master Parallel and peripheral configuration
modes, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.

DIN

During Slave Serial or Master Serial configuration modes,
this is the serial configuration data input receiving data on
the rising edge of CCLK.

During parallel configuration modes, this is the D0 input.
After configuration, DIN is a user-programmable I/O pin.

DOUT

During configuration in any mode, this is the serial
configuration data output that can drive the DIN of daisy-
chained slave LCA devices. DOUT data changes on the
falling edge of CCLK, 1.5 CCLK periods after it was
received at the DIN input. After configuration, DOUT is a
user-programmable I/O pins.

Unrestricted User-Programmable I/O Pins

I/O

A pin that can be configured to be input and/or output after
configuration is completed. Before configuration is
completed, these pins have an internal high-value pull-up
resistor that defines the logical level as High.

Pin Descriptions

Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a

50-k

to 100-k

pull-up resistor.

Absolute Maximum Ratings

Operating Conditions

DC Characteristics Over Operating Conditions

Symbol

Description

Units

Supply voltage relative to GND

-0.5 to +7.0

Input voltage with respect to GND

-0.5 to V

+0.5

Voltage applied to 3-state output

-0.5 to V

+0.5

STG

Storage temperature (ambient)

-65 to +150

SOL

Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)

+260

Junction temperature in plastic packages

+125

Junction temperature in ceramic packages

+150

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.

Symbol

Description

Min

Max

Units

Supply voltage relative to GND

Commercial:

C to 70

4.75

5.25

Supply voltage relative to GND

Industrial:

-40

C to 85

4.5

5.5

Supply voltage relative to GND

Military:

-55

C to 125

4.5

5.5

IHT

High-level input voltage -- TTL configuration

2.0

ILT

Low-level input voltage -- TTL configuration

0.8

IHC

High-level input voltage -- CMOS configuration

70%

100%

ILC

Low-level input voltage -- CMOS configuration

20%

Input signal transition time

250

Symbol

Description

Min

Max

Units

High-level output voltage @ I

= -8.0 mA, V

min

3.86

Low-level output voltage @ I

= 8.0 mA, V

max (Note 1)

0.4

CCO

Quiescent LCA supply current (Note 1)

Leakage current

-10

+10

Input capacitance (sample tested)

RIN

Pad pull-up (when selected) @ V

= 0V (sample tested)

0.02

0.25

Note: 1. With no output current loads, all package pins at V

or GND, and the LCA configured with a MakeBits tie option.

XC5200 Logic Cell Array Family

Preliminary

Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from
benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating
conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the
XACT timing calculator and used in the simulator.

Speed Grade

-6

-5

-4

Description

Symbol

Device

Max

(ns)

Max

(ns)

Max

(ns)

Global Signal Distribution

From pad through global buffer, to any clock (CK)

BUFG

XC5202

XC5204

XC5206

9.4

8.8

XC5210

9.4

8.8

XC5215

Internal Clock to Output Pad Delay

From clock (CK) to output pad (fast), using direct connect
between Q and output (O)

OKPOF

XC5202

XC5204

XC5206

9.9

8.9

XC5210

9.9

8.9

XC5215

From clock (CK) to output pad (slew-limited), using direct
connect between Q and output (O)

OKPOS

XC5202

XC5204

XC5206

14.8

12.7

XC5210

14.8

12.7

XC5215

Note:

Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.

Longline Switching Characteristic Guidelines

Speed Grade

-6

-5

-4

Description

Symbol

Device

Max

(ns)

Max

(ns)

Max

(ns)

TBUF driving a Longline

I to Longline, while TS is Low; i.e., buffer is constantly active

XC5202

XC5204

XC5206

4.0

3.6

XC5210

4.0

3.6

XC5215

TS going Low to Longline going from floating High or Low to
active Low or High

XC5202

XC5204

XC5206

5.3

4.8

XC5210

5.3

4.8

XC5215

TS going High to TBUF going inactive, not driving Longline

OFF

XC5202

XC5204

XC5206

2.4

2.2

XC5210

2.4

2.2

XC5215

Note:

Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.

TBUF

XC5200 Logic Cell Array Family

Preliminary

Guaranteed Input and Output Parameters (Pin-to-Pin)

All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also
be derived indirectly from the Global Buffer specifications. The XACT delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.

Speed Grade

-6

-5

-4

Description

Symbol

Device

Max

(ns)

Max

(ns)

Max

(ns)

Global Clock to Output Pad (fast)

ICKOF

(Max)

XC5202

XC5204

XC5206

17.2

15.4

XC5210

17.2

15.4

XC5215

Global Clock to Output Pad (slew-limited)

ICKO

(Max)

XC5202

XC5204

XC5206

21.7

19.0

XC5210

21.7

19.0

XC5215

Input Set-up Time (no delay) to CLB Flip-Flop

PSUF

(Min)

XC5202

XC5204

XC5206

1.2

0.5

XC5210

1.2

0.5

XC5215

Input Hold Time (no delay) to CLB Flip-Flop

PHF

(Min)

XC5202

XC5204

XC5206

3.0

2.5

XC5210

3.0

2.5

XC5215

Input Set-up Time (with delay) to CLB Flip-Flop

PSU

(Min)

XC5202

XC5204

XC5206

7.5

6.4

XC5210

7.5

6.4

XC5215

Input Hold Time (with delay) to CLB Flip-Flop

(Min)

XC5202

XC5204

XC5206

XC5210

XC5215

Note:

These measurements assume that the flip-flop has a direct connect to or from the IOB. XACT-Performance can be
used to assure that direct connects are used.

When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.

Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.

Global Clock-to-Output Delay

BUFG

Direct

Connect

IOB

CLB

Global Clock-to-Output Delay

BUFG

Direct

Connect

IOB

CLB

Input

Set-up
& Hold

Time

BUFG

IOB

Direct

Connect

CLB

Input

Set-up
& Hold

Time

BUFG

IOB

Direct

Connect

CLB

Input

Set-up
& Hold

Time

BUFG

IOB

Direct

Connect

CLB

Input

Set-up
& Hold

Time

BUFG

IOB

Direct

Connect

CLB

IOB Switching Characteristic Guidelines

Speed Grade

-6

-5

-4

Description

Symbol

Max

(ns)

Max

(ns)

Max

(ns)

Input

Propagation Delays from CMOS or TTL Levels

Pad to I (no delay)

5.4

4.9

Pad to I (with delay)

PID

11.1

10.2

Output

Propagation Delays to CMOS or TTL Levels

Output (O) to Pad (fast)

OPF

4.6

4.5

Output (O) to Pad (slew-limited)

OPS

9.4

8.3

3-state to Pad active (fast)

TSONF

6.9

6.6

3-state to Pad active (slew-limited)

TSONS

11.6

10.4

Internal GTS to Pad active (fast)

GTSF

17.7

15.9

Internal GTS to Pad active (slew-limited)

GTSS

22.3

19.7

Note:

Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce,
see pages 8-8 through 8-10 of the 1994 Xilinx Programmable Logic Data Book.

Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.

XC5200 Logic Cell Array Family

Preliminary

CLB Switching Characteristic Guidelines

Speed Grade

-6

-5

-4

Description

Symbol

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Combinatorial Delays

F inputs to X output

ILO

5.5

4.5

DI inputs to DO output (Logic-Cell Feedthrough)

IDO

4.2

3.3

F inputs via F5_MUX to DO output

IMO

7.1

5.7

Carry Delays

Incremental delay per bit

0.7

0.6

Carry-in overhead from DI

CYDI

1.7

1.5

Carry-in overhead from F

CYL

3.6

3.2

Carry-out overhead to DO

CYO

3.9

3.1

Sequential Delays

Clock (CK) to out (Q) (Flip-Flop)

CKO

5.4

4.4

Gate (Latch enable) going active to out (Q)

8.6

6.8

Set-up Time Before Clock (CK)

F inputs

ICK

2.1

1.5

F inputs via F5_MUX

MICK

3.6

2.7

DI input

DICK

0.5

0.3

CE input

EICK

1.2

0.9

Hold Times After Clock (CK)

F inputs

CKI

F inputs via F5_MUX

CKMI

DI input

CKDI

CE input

CKEI

Clock Widths

Clock High Time

6.0

Clock Low Time

6.0

Reset Delays

Width (High)

CLRW

6.0

Delay from CLR to Q (Flip-Flop)

CLR

7.3

5.8

Delay from CLR to Q (Latch)

CLRL

6.1

4.8

Global Reset Delays (see Note 2)

Width (High)

GCLRW

6.0

Delay from internal GCLR to Q

GCLR

12.4

10.2

Note:

The CLB K to Q output delay (T

CKO

) of any CLB, plus the shortest possible interconnect delay, is always longer than the

Data In hold-time requirement (T

CKDI

) of any CLB on the same die.

Timing is based upon the XC5210 device. For other devices, see XACT Timing Calculator.

Figure 19. XC5206 CLB-to-Pad Relationship (Detail)

Note:

Pad numbers (1, 2, ..., 148) refer to die pads, not external device pins. Also see the XC5206 pinout table on pages 36-37.

R2C1

R3C1

R4C1

R5C1

R6C1

R7C1

R8C1

R9C1

R10C1

R11C1

R12C1

R13C1

R14C1

19
20

21
22
23

24
25
26

27
28
29

30
31
32

33
34

35
36

37
38
39

40
41
42

43
44
45

46
47
48

49
50
51

52
53
54

55
56

57
58

59
60
61

62
63

64
65
66

67
68
69

70
71
72

73
74
75

76
77
78

79
80
81

82
83
84

85
86

87
88

89
90
91

92
93

R14C2

R14C3

R14C4

R14C5

R14C6

R14C7

R14C8

R14C9

R14C10

R14C11

R14C12

R14C13

R14C14

129
128

127
126
125

124
123
122

121
120
119

118
117
116

115
114

113
112

111
110

109
108
107

106
105
104

103
102

101
100
99

98
97
96

95
94

R2C14

R3C14

R4C14

R5C14

R6C14

R7C14

R8C14

R9C14

R10C14

R11C14

R12C14

R13C14

R14C14

R1C1

R1C2

R1C3

R1C4

R1C5

R1C6

R1C7

R1C8

R1C9

R1C10

R1C11

R1C12

R1C13

R1C14

18
17

16
15

14
13

12
11
10

9
8
7

6
5
4

3
2
1

148
147
146

145
144
143

142
141
140

139
138

137
136
135

134
133
132

131

130

R1C1

R14C1

R1C14

Left

Bottom

Right

Top

Figure 21. XC5210 CLB-to-Pad Relationship (Detail)

R2C1

R3C1

R4C1

R5C1

R6C1

R7C1

R8C1

R9C1

R10C1

R11C1

R12C1

R13C1

R14C1

R15C1

R16C1

R17C1

R18C1

25
26

27
28
29

30
31
32

33
34
35

36
37
38

39
40
41

42
43
44

45
46

47
48

49
50
51

52
53
54

55
56
57

58
59
60

61
62
63

64
65
66

67
68
69

70
71
72

73
74

75
76

77
78
79

80
81
82

83
84
85

86
87
88

89
90

91
92
93

94
95
96

97
98
99

100
101
102

103
104
105

106
107
108

109
110

111
112

113
114
115

116
117
118

119
120
121

122
123

R18C2

R18C3

R18C4

R18C5

R18C6

R18C7

R18C8

R18C9

R18C10

R18C11

R18C12

R18C13

R18C14

R18C15

R18C16

R18C17

171
170

169
168
167

166
165
164

163
162
161

160
159
158

157
156
155

154
153
152

151
150

149
148

147
146

145
144
143

142
141
140

139
138
137

136
135

134
133
132

131
130
129

128
127
126

125
124

R2C18

R3C18

R4C18

R5C18

R6C18

R7C18

R8C18

R9C18

R10C18

R11C18

R12C18

R13C18

R14C18

R15C18

R16C18

R17C18

R18C18

R1C1

R1C2

R1C3

R1C4

R1C5

R1C6

R1C7

R1C8

R1C9

R1C10

R1C11

R1C12

R1C13

R1C14

R1C15

R1C16

R1C17

R1C18

24
23

22
21
20

19
18
17

16
15
14

13
12

11
10

9
8
7

6
5
4

3
2
1

196
195
194

193
192
191

190
189
188

187
186

185
184
183

182
181
180

179
178
177

176
175
174

173

172

R1C1

R18C1

R18C18

R1C18

Left

Bottom

Right

Top

Note:

Pad numbers (1, 2, ..., 196) refer to die pads, not external device pins. Also see the XC5210 pinout table on pages 38-39.

XC5200 Logic Cell Array Family

Preliminary (v1.0)

Pin Description

PC84

PQ160

PQ208

PG191

Boundary

Scan Order

VCC

142

183

I/O (A8)

143

184

I/O (A9)

144

185

I/O

145

186

I/O

146

187

I/O

188

102

I/O

189

105

I/O (A10)

147

190

111

I/O (A11)

148

191

114

I/O

149

192

117

10.

I/O

150

193

123

GND

151

194

195*

196*

11.

I/O

152

197

126

12.

I/O

153

198

129

13.

I/O (A12)

154

199

138

14.

I/O (A13)

155

200

141

15.

I/O

156

201

150

16.

I/O

157

202

153

17.

I/O (A14)

158

203

162

18.

I/O (A15)

159

204

165

VCC

160

205

206*

207*

208*

GND

19.

GCK1 (A16, I/O)

174

20.

I/O (A17)

177

21.

I/O

183

22.

I/O

186

23.

I/O (TDI)

189

24.

I/O (TCK)

195

25.

I/O

198

26.

I/O

201

12*

13*

GND

27.

I/O

207

28.

I/O

210

29.

I/O (TMS)

213

30.

I/O

219

31.

I/O

222

32.

I/O

225

33.

I/O

234

34.

I/O

237

35.

I/O

246

36.

I/O

249

GND

VCC

D10

37.

I/O

C10

255

38.

I/O

B10

258

39.

I/O

261

40.

I/O

A10

267

41.

I/O

A11

270

42.

I/O

C11

273

43.

I/O

B11

279

44.

I/O

A12

282

45.

I/O

B12

285

46.

I/O

A13

291

GND

C12

38*

39*

47.

I/O

A15

294

48.

I/O

C13

297

49.

I/O

B14

303

50.

I/O

A16

306

51.

I/O

B15

309

52.

I/O

C14

315

53.

I/O

A17

318

54.

I/O

B16

321

55.

M1 (I/O)

C15

330

GND

D15

56.

M0 (I/O)

A18

333

51*

52*

53*

54*

VCC

D16

57.

M2 (I/O)

C16

336

58.

GCK2 (I/O)

B17

339

59.

I/O (HDC)

E16

348

60.

I/O

C17

351

61.

I/O

D17

354

62.

I/O

B18

360

63.

I/O (LDC)

E17

363

64.

I/O

F16

372

65.

I/O

C18

375

GND

G16

66.

I/O

E18

378

67.

I/O

F18

384

68.

I/O

G17

387

69.

I/O

G18

390

70.

I/O

H16

396

71.

I/O

H17

399

72.

I/O

H18

402

73.

I/O

J18

408

74.

I/O

J17

411

75.

I/O (ERR, INIT)

J16

414

VCC

J15

GND

K15

76.

I/O

K16

420

Pin Description

PC84

PQ160

PQ208

PG191

Boundary

Scan Order

XC5206 Pinouts

* Indicates unconnected package pins.

Leading number refers to bonded pad, shown in Figure 19.

XC5206 Pinouts (continued)

77.

I/O

K17

423

78.

I/O

K18

426

79.

I/O

L18

432

80.

I/O

L17

435

81.

I/O

L16

438

82.

I/O

M18

444

83.

I/O

M17

447

84.

I/O

N18

450

85.

I/O

P18

456

GND

M16

91*

92*

86.

I/O

T18

459

87.

I/O

P17

468

88.

I/O

N16

471

89.

I/O

T17

480

90.

I/O

R17

483

91.

I/O

P16

486

92.

I/O

U18

492

93.

I/O

100

T16

495

GND

101

R16

102*

DONE

103

U17

104*

105*

VCC

106

R15

107*

PROG

108

V18

94.

I/O (D7)

109

T15

504

95.

GCK3 (I/O)

110

U16

507

96.

I/O

111

T14

516

97.

I/O

112

U15

519

98.

I/O (D6)

113

V17

522

99.

I/O

114

V16

528

100. I/O

115

T13

531

101. I/O

116

U14

534

117*

118*

GND

119

T12

102. I/O

120

U13

540

103. I/O

121

V13

543

104. I/O (D5)

122

U12

552

105. I/O (CS0)

123

V12

555

106. I/O

124

T11

558

107. I/O

125

U11

564

108. I/O

126

V11

567

109. I/O

127

V10

570

110. I/O (D4)

128

U10

576

111.

I/O

129

T10

579

VCC

100

130

R10

GND

101

131

Pin Description

PC84

PQ160

PQ208

PG191

Boundary

Scan Order

112. I/O (D3)

102

132

588

113. I/O (RS)

103

133

591

114. I/O

104

134

600

115. I/O

105

135

603

116. I/O

136

612

117. I/O

137

615

118. I/O (D2)

106

138

618

119. I/O

107

139

624

120. I/O

108

140

627

121. I/O

109

141

630

GND

110

142

143*

144*

122. I/O

111

145

636

123. I/O

112

146

639

124. I/O (D1)

113

147

642

125.

I/O (RCLK-
BUSY/RDY)

114

148

648

126. I/O

115

149

651

127. I/O

116

150

654

128. I/O (D0, DIN)

117

151

660

129. I/O (DOUT)

118

152

663

CCLK

119

153

VCC

120

154

155*

156*

157*

158*

130. (I/O) TDO

121

159

GND

122

160

131.

I/O (A0, WS)

123

161

132.

I/O (GCK4, A1)

124

162

133. I/O

125

163

134. I/O

126

164

135.

I/O (CS1, A2)

127

165

136. I/O (A3)

128

166

137. I/O

129

167

138. I/O

130

168

169*

170*

GND

131

171

139. I/O

132

172

140. I/O

133

173

141. I/O (A4)

134

174

142. I/O (A5)

135

175

143. I/O

176

144. I/O

136

177

145. I/O

137

178

146. I/O

138

179

147. I/O (A6)

139

180

148. I/O (A7)

140

181

GND

141

182

Pin Description

PC84

PQ160

PQ208

PG191

Boundary

Scan Order

Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 666 = BSCAN.UPD

XC5200 Logic Cell Array Family

Preliminary (v1.0)

Pin Description

PC84

PQ160

PQ208

PG223

PQ240

Boundary

Scan Order

VCC

142

183

212

I/O (A8)

143

184

213

111

I/O (A9)

144

185

214

114

I/O

145

186

215

117

I/O

146

187

216

123

I/O

188

217

126

I/O

189

218

129

219*

I/O (A10)

147

190

220

135

I/O (A11)

148

191

221

138

VCC

222

I/O

223

141

10.

I/O

224

150

11.

I/O

149

192

225

153

12.

I/O

150

193

226

162

GND

151

194

227

13.

I/O

195

228

165

14.

I/O

196

229

171

15.

I/O

152

197

230

174

16.

I/O

153

198

231

177

17.

I/O (A12)

154

199

232

183

18.

I/O (A13)

155

200

233

186

19.

I/O

234

189

20.

I/O

235

195

21.

I/O

156

201

236

198

22.

I/O

157

202

237

201

23.

I/O (A14)

158

203

238

210

24.

I/O (A15)

159

204

239

213

VCC

160

205

240

206*

207*

208*

GND

25.

GCK1 (A16, I/O)

222

26.

I/O (A17)

225

27.

I/O

231

28.

I/O

234

29.

I/O (TDI)

237

30.

I/O (TCK)

243

31.

I/O

246

32.

I/O

249

33.

I/O

255

34.

I/O

258

35.

I/O

261

36.

I/O

267

GND

37.

I/O

270

38.

I/O

273

39.

I/O (TMS)

279

40.

I/O

282

VCC

41.

I/O

285

42.

I/O

291

22*

43.

I/O

294

44.

I/O

297

45.

I/O

306

46.

I/O

309

47.

I/O

318

48.

I/O

321

GND

VCC

D10

49.

I/O

C10

327

50.

I/O

B10

330

51.

I/O

333

52.

I/O

A10

339

53.

I/O

A11

342

54.

I/O

C11

345

37*

55.

I/O

D11

351

56.

I/O

D12

354

VCC

57.

I/O

B11

357

58.

I/O

A12

363

59.

I/O

B12

366

60.

I/O

A13

369

GND

C12

61.

I/O

D13

375

62.

I/O

D14

378

63.

I/O

B13

381

64.

I/O

A14

387

65.

I/O

A15

390

66.

I/O

C13

393

67.

I/O

B14

399

68.

I/O

A16

402

69.

I/O

B15

405

70.

I/O

C14

411

71.

I/O

A17

414

72.

I/O

B16

417

73.

M1 (I/O)

C15

426

GND

D15

74.

M0 (I/O)

A18

429

51*

52*

53*

54*

VCC

D16

75.

M2 (I/O)

C16

432

76.

GCK2 (I/O)

B17

435

77.

I/O (HDC)

E16

444

78.

I/O

C17

447

79.

I/O

D17

450

80.

I/O

B18

456

81.

I/O (LDC)

E17

459

82.

I/O

F16

462

83.

I/O

C18

468

84.

I/O

D18

471

85.

I/O

F17

474

86.

I/O

E15

480

87.

I/O

F15

483

GND

G16

88.

I/O

E18

486

89.

I/O

F18

492

90.

I/O

G17

495

91.

I/O

G18

504

VCC

92.

I/O

H16

507

93.

I/O

H17

510

83*

94.

I/O

G15

516

95.

I/O

H15

519

96.

I/O

H18

522

97.

I/O

J18

528

98.

I/O

J17

531

99.

I/O (ERR, INIT)

J16

534

VCC

J15

GND

K15

100. I/O

K16

540

Pin Description

PC84

PQ160

PQ208

PG223

PQ240

Boundary

Scan Order

XC5210 Pinouts

* Indicates unconnected package pins.

Leading number refers to bonded pad, shown in Figure 21.

101. I/O

K17

543

102. I/O

K18

546

103. I/O

L18

552

104. I/O

L17

555

105. I/O

L16

558

98*

106. I/O

L15

564

107. I/O

M15

100

567

VCC

101

108. I/O

M18

102

570

109. I/O

M17

103

576

110. I/O

N18

104

579

111.

I/O

P18

105

588

GND

M16

106

112. I/O

N15

107

591

113. I/O

P15

108

600

114. I/O

N17

109

603

115. I/O

R18

110

606

116. I/O

T18

111

612

117. I/O

P17

112

615

118. I/O

N16

113

618

119. I/O

T17

114

624

120. I/O

R17

115

627

121. I/O

P16

116

630

122. I/O

U18

117

636

123. I/O

100

T16

118

639

GND

101

R16

119

102*

DONE

103

U17

120

104*

105*

VCC

106

R15

121

107*

PROG

108

V18

122

124. I/O (D7)

109

T15

123

648

125. GCK3 (I/O)

110

U16

124

651

126. I/O

111

T14

125

660

127. I/O

112

U15

126

663

128. I/O

R14

127

666

129. I/O

R13

128

672

130. I/O (D6)

113

V17

129

675

131. I/O

114

V16

130

678

132. I/O

115

T13

131

684

133. I/O

116

U14

132

687

134. I/O

117

V15

133

690

135. I/O

118

V14

134

696

GND

119

T12

135

136. I/O

R12

136

699

137. I/O

R11

137

708

138. I/O

120

U13

138

711

139. I/O

121

V13

139

714

VCC

140

140. I/O (D5)

122

U12

141

720

141. I/O (CS0)

123

V12

142

723

143*

142. I/O

124

T11

144

726

143. I/O

125

U11

145

732

144. I/O

126

V11

146

735

145. I/O

127

V10

147

738

146. I/O (D4)

128

U10

148

744

147. I/O

129

T10

149

747

VCC

100

130

R10

150

GND

101

131

151

148. I/O (D3)

102

132

152

756

Pin Description

PC84

PQ160

PQ208

PG223

PQ240

Boundary

Scan Order

149. I/O (RS)

103

133

153

759

150. I/O

104

134

154

768

151. I/O

105

135

155

771

152. I/O

136

156

780

153. I/O

137

157

783

158*

154. I/O (D2)

106

138

159

786

155. I/O

107

139

160

792

VCC

161

156. I/O

108

140

162

795

157. I/O

109

141

163

798

158. I/O

164

804

159. I/O

165

807

GND

110

142

166

160. I/O

167

810

161. I/O

168

816

162. I/O

143

169

819

163. I/O

144

170

822

164. I/O

111

145

171

828

165. I/O

112

146

172

831

166. I/O (D1)

113

147

173

834

167.

I/O (RCLK-
BUSY/RDY)

114

148

174

840

168. I/O

115

149

175

843

169. I/O

116

150

176

846

170.

I/O (D0, DIN)

117

151

177

855

171. I/O (DOUT)

118

152

178

858

CCLK

119

153

179

VCC

120

154

180

155*

156*

157*

158*

172. I/O (TDO)

121

159

181

GND

122

160

182

173.

I/O (A0, WS)

123

161

183

174.

GCK4 (I/O, A1)

124

162

184

175. I/O

125

163

185

176. I/O

126

164

186

177.

I/O (CS1, A2)

127

165

187

178. I/O (A3)

128

166

188

179. I/O

189

180. I/O

190

181. I/O

129

167

191

182. I/O

130

168

192

183. I/O

169

193

184. I/O

170

194

195*

GND

131

171

196

185. I/O

132

172

197

186. I/O

133

173

198

187. I/O

199

188. I/O

200

VCC

201

189. I/O (A4)

134

174

202

190. I/O (A5)

135

175

203

204*

191. I/O

176

205

192. I/O

136

177

206

193. I/O

137

178

207

194. I/O

138

179

208

195. I/O (A6)

139

180

209

102

196. I/O (A7)

140

181

210

105

GND

141

182

211

Pin Description

PC84

PQ160

PQ208

PG223

PQ240

Boundary

Scan Order

XC5210 Pinouts (continued)

Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 666 = BSCAN.UPD

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XC5210-6PQ208C

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XC5210-6PQ208C